VIVADO block port design question

You can’t (easily) use AXI lite. With AXI lite you have to write all the data you want to transfer to registers. Depending on the size of your array, you may reach a limit for the number or registers you can have. This is also slow and inefficient and should not be used for transferring arrays.
AXI lite is generally only used for reading/writing control and status data.

The easiest way to implement your design (in my opinion) is to change the a,b, and c ports to AXI STREAM, then add a DMA to manage the data transfer.

You can follow these two tutorials:
This only uses an input and output (a,b) so you need to a third AXI stream interface for “c” in your design.
Each DMA can have 1x input steam, 1x output stream, so you need 2 DMAs (one with 1 input stream and an output stream, and the other with 1x input stream.