VIVADO block port design question

[hsuharry12]

Thank you for your reply, we based on the teaching of your reply,

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

It is found that the “AXI4-Stream Data FIFO” link will conflict with the input and output interface we designed (sda), so we refer to another link

Tutorial: using a HLS stream IP with DMA (Part 2: Vivado design)

This is the second part of a tutorial that will show how to create a HLS IP and use it with an AXI DMA controlled by PYNQ. Part 1 of this tutorial showed how to build the HLS IP. This part 2 shows how to build the hardware and use the IP with PYNQ. Part 3 shows how to use the design with PYNQ. This tutorial is based on the v2.7 PYNQ image and will use Vivado 2020.2 (required for PYNQ v2.7). Vitis HLS 2020.2 will be used to build the HLS IP. If you are using a different PYNQ version you should…

, there is no “AXI4-Stream Data FIFO” in this teaching, which can make “sda” connect to the input and output of DMA smoothly (Fig.1), but according to this teaching to the end we have the following two serious warnings (Fig.2).

After some searching we found that TLAST seems to be related to “hls::axis<float, 0, 0, 0>” according to this link
https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/master/Interface/Streaming/using_axi_stream_with_struct/example_test.cpp,
However, the programming language we wrote is C language, and I don’t know if it can match.