PL FCLK0 changes as soon as overlay loads bitfile


I am observing following issue

  1. I have configured Zynq PS to have PS-PL fabric clock FCLK0 as 200 Mhz
    The bit-file is successfully generated
  2. In the notebook when I read the fclk0 before loading bitfile it shows it as 199.99Mhz
  3. After i load the bitfile in the notebook, it shows frequency of fclk0 as
    FCLK0: 374.996250MHz

When I try to set frequency to 200 Mhz
from pynq import Clocks
Clocks.fclk0_mhz = 200

it gives me following warning
/usr/local/lib/python3.6/dist-packages/pynq/ UserWarning: Setting frequency to the closet possible value 214.28357MHz.
round(freq_high / q0, 5)))

Any hints on why my FCLK0 frequency is changing when i load bit file
How can I set frequency accurately to 200 Mhz

Would you be able to share the .tcl or .hwh file you are using? My best guess is that the FCLK is being configured to derive from a different PLL which has been configured to run at 1500 MHz hence the restrictions you are seeing. Can you also screenshot the clock configuration window in vivado?


Hi Peter,

Please find attached the zip file for .hwh (98.8 KB)

Also snapshot of clock configuration window is attached


Hi Peter,

Can you suggest me something here.
The HWH file is attached in previous reply

Sorry it took so long to get back to you.

At present the PYNQ framework will only consider the IOPLL when setting a clock frequency and for the Ultra96 standard design this is set to 1500 MHz meaning that only divisions of 1500 will get set correctly. It also won’t try to reconfigure PLLs has that can have broader system implications.

The easiest way to get a 200 MHz clock reliably is to add a clock wizard in the fabric and generate a new 200 MHz clock from the default fabric clock of 100 MHz.

Supporting other PLL settings is something we can look into in the future.

Out of interest, did you recreate a BOOT.BIN or otherwise force the clocks to 200 MHz prior to loading the bitstream?


Hi Peter,

Thanks for your guidance. It has helped me to progress on using PYNQ for design validation. I have been using clocking wizard to generate 200 Mhz clock as otherwise I get errors for CSI2 traffic in VDMA. For your question, I recreated BOOT.BIN. I did not force clocks prior to loading bitstream

One thing I struggle with is how to handle interrupts in PYNQ…
For example - I want to write interrupt handlers which are running in parallel to my main code and
keep servicing interrupts. I find it confusing. Any advice on example code or some documentation/ template code which you can refer will help me a lot.

Best Regards