Zcu104 - error while synthesizing an ip

Support
1

Hi,
I am trying to create my own IP on vitis HLS, to configure with a PYNQ system on a ZCU104 board.
When I use the #prage HLS UNROLL, I ma not able to sythesize my code and I am getting the following errors.
while executing
“source C:/Users/WS2-Praseetha/Pictures/loop_pipeline2/loop_pipeline/solution1/csynth.tcl”
invoked from within
This is my .h file
#ifndef LOOP_PIPELINE_H
#define LOOP_PIPELINE_H
#include
#include
using namespace std;
#include “hls_stream.h”
#include “ap_int.h”
#define DIM 7
#define DIM01 100
#define DIM02 100

#include
#include
using namespace std;

void loop_pipeline(int N,int rowss[DIM01], int coll[DIM01], int vall[DIM01],int irad[100][100]);

#endif

This is the loops I want to unroll
l_1: for( y = 0; y <100; y ++)

  {
    #pragma HLS UNROLL

l_2:for( x = 0; x <100; x++)

     {
       #pragma HLS UNROLL
2

First try this:
image fun.cpp (457 Bytes) fun.h (216 Bytes) fun_tb.cpp (329 Bytes)

it’s working?
Yes → You have something wrong in your code, and you posted too small sample for us to debug. Read red errors in console for more info.
No → You could have no license/broken Vitis etc…

PS. fun2 is top function
PS2. If you unroll L_1, L_2 is automatically unrolled

3

This isn’t really a PYNQ question. You may be better posting this on the Xilinx forums.

Cathal