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RuntimeError: DMA channel not started on ZCU 111
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3
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66
|
April 8, 2025
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RFSoC 4x2: How to locked clk_in0 to dout8 through LMK04828 and then give to FPGA PL SYS REFCLK?
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1
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78
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April 8, 2025
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RFSoC 4x2 ADC tile
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3
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196
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April 8, 2025
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Cannot connect to PYNQ on ZCU111
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3
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55
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April 7, 2025
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DMA missing data due to delay in between dma_recv.transfer()
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1
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48
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April 7, 2025
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Running PYNQ on Pycharm or other IDE for Python
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4
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1087
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April 4, 2025
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PYNQ-z2 pmod ad1, FFT
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0
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21
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April 2, 2025
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Discrepancy between time calculated by vitis hls report and that calculated on PYNQ
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3
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35
|
April 2, 2025
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Building linux in yocto or petalinux
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0
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157
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April 1, 2025
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Typo in website tagline!
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1
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23
|
April 1, 2025
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Receive Cyclic DMA
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1
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132
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April 1, 2025
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Questions regarding MTS Implementation
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0
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128
|
April 1, 2025
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Frequency Detection and Bit Mapping Using PMOD AD1 ADC and FFT on PYNQ Z2
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1
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103
|
March 31, 2025
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How to compile custom overlay with integrated DPU on pynq
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4
|
527
|
March 28, 2025
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Change Threshold ADC
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0
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26
|
March 27, 2025
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Pynqzu failed to install ros2 humble
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1
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270
|
March 27, 2025
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Failed to create application project
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1
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63
|
March 27, 2025
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AXI stream of struct
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9
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159
|
March 27, 2025
|
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I2c connection timing out
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6
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203
|
March 26, 2025
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Problem with I2C Interface with DAC MCP4725 through Arduino pins
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2
|
58
|
March 26, 2025
|
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Latency in DRAM-RF data converter path
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0
|
33
|
March 26, 2025
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Pynq z2 fft
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1
|
117
|
March 25, 2025
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DRAM to RF data converter
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0
|
20
|
March 24, 2025
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TLAST Signal Not Generated in RTL Files (HLS4ML + Vitis HLS and pynq Z2)
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3
|
110
|
March 24, 2025
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Pre trained CNN deployment on Pynq ZU board
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1
|
87
|
March 24, 2025
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Zocl-drm axi:zyxclmm_drm: IRQ index 0 not found
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0
|
86
|
March 21, 2025
|
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Can not debug in Vitis even if I can "program device" in vivado
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1
|
128
|
March 20, 2025
|
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Reaching out to the Ultra96 PYNQ community
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|
0
|
24
|
March 19, 2025
|
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Other third party overlays for PYNQ Z1
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|
1
|
39
|
March 18, 2025
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Custom operation on Deep neural network using pynq Z2
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0
|
32
|
March 14, 2025
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