ADC and DAC in TileState 7

Hello everyone,
I am trying to modify slightly the rfsoc qsfp exemple. I first modified it by using 2 DAC and 2 ADC and it worked fine. Then, I tried to decrease the sampling rate to 1.2288 GSps and also slightly modified the DAC and ADC settings ( Interpolator and decimator values set to 1 and only real data and not IQ). All the different settings can be found on the images attached. The bitstream generated succesfully, however, when I go to Pynq and try to initialize the 2 ADC and DAC, their tile state is 7 and I thus can’t do anything with them. Would someone have any idea where the problem could come from?