I have a few question regarding adding the DPU using Vitis flow to the base Pynq Overlay. What I have tried so far does not seem to work.
→ Generate block design for the base overlay.
→ Add more PL clocks (600 MHz for dpu_2x_clock)
→ Enable more PS interfaces S_AXI_HP2, S_AXI_HP3, M_AXI_HP etc. as needed by the DPU IP (in total 3 slaves are needed by the DPU).
→ convert project to a platform project and export clocks, interfaces and interrupt (which one?) in the platform for use in Vitis.
→ Use Vitis to generate the .xclbin file after adding DPU.
→ open Vitis hardware link design and export board design .tcl file and .hwh file.
→ Copy over to board Pynq image and run DPU example. DPU crashes whereas the DPU-PYNQ overlay works as well as my custom DPU overlay. But starting with the Base overlay block design (I need the HDMI), things do not seem to work.
So the question is what am I missing? For my custom design and the DPU-PYNQ design I do not modify the image in any way. Maybe I need a custom device tree component.
Another question is where do I connect the DPU interrupt output?
Also, how are the modified PS settings taken into account by the PYNQ python classes? As the PS settings for the DPU PYNQ overlay are different then the base overlay. Is the FSBL auto-updated, or do I need to change things and if so how?
Thanks for your help.