Deploying custom DPU design on zcu104

Support
1

Hello Guys,

I want to deploy a custom DPU design on m zcu104 because I want to use some GPIO.

I first tried to use this repo as a baseline to create the design and quickly realised that the zcu104 has less LUTs and LUTRam than the zcu102.

I now build my design with this
Repo as a baseline and successfully created a .bit and .hwh file. I am missing the .xclbin File. How do I create this and why do I need it ?

Is there maybe a better baseline to create my hardware design, maybe even something from Xilinx ?

Also is the way the arch.json is created recommended ?

Thank you for your help!
Greetings
Henning

2

Hi Henning,

To generate an xclbin you would have to follow the Vitis flow and build a Vitis platform from your hardware design. The Vitis AI Runtime (VART) library that pynq_dpu uses under the hood needs the xclbin specified by the path in /etc/vart.conf.

You can check how we do it in the dpu-pynq repo, the flow is very similar to the Vitis flow I previously linked.

I believe the arch.json file is generated by Vitis and is specific to your DPU configuration. You will need it when compiling models to run on your design.

Thanks
Shawn

3

I tried that, but if I change the zcu102 Design to a zcu104 it does not fit the FPGA anymore. So I cant follow the Vitis flow.

I tried it with the resources I linked, but the PetaLinux fails to build. So I am clueless how I should progress now.

4

What DPU configs are you using? To fit it into your design, you could try to reduce the size of the DPU or reduce the number of DPU cores. I think the tutorial is using the largest DPU size B4096 and 2 cores.

Thanks
Shawn

5

Yes I think it uses the largest size.

Can I somewhere find the config the prebuild petalinux dpu for the zcu104 uses, because I want to benchmark vitis ai and dont want to reduce the dpu to much.

6

You can check the config in dpu-pynq, it should match the model zoo benchmark.

Thanks
Shawn

7

So I managed to fit the hardware design on the zcu104 with Vivado. Now I need to create a Vitis project. You linked this flow, but I dont see where I can load my vivado project? I thought the xsa file is enough to create a Vitis project? I am sorry I have never worked with Vitis before.

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8

There is a section on integrating a custom platform in 5.4 in the Vitis flow, with a bit more info on platforms there. You could also potentially integrate your design by using the dpu-pynq makefiles if you replaced the dpu.tcl with your design (including the platform attribute settings).

Thanks
Shawn

9

That’s interesting. I didnt see that .tcl. I just need to add a gpio + slice and and external signal and the corresponding .xdc file. I will try to update the .tcl to my needs maybe I can accomplish that. Thanks for your help already. I will report back if I get it working.

Edit:
I managed to get it working. I now got the .bit, .hwh and .xclbin. Thank you very much!
I pushed my changes to this repo if you want to check it out: GPIO-Added

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