I want to create a custom platform that consists of the DPU, camera interface, pmod gpio, and custom accelerator image processing IP core.
I have learned and checked several tutorials, such as Step 1: Create the Vivado Hardware Design and Generate XSA — Vitis™ Tutorials 2021.1 documentation
Creating a DPU-Compatible Platform for PYNQ - MakarenaLabs
I followed the tutorial DPU-PYNQ/boards at master · Xilinx/DPU-PYNQ · GitHub, to generate the dpu overlay, and it works for kv260_som. in my observation, the script creates the vivado project with several clocks and implements dpu outside with vitis flow, is it correct, right?
I think I need to clarify some of my understanding, and I have several questions.
My understanding now, so we need to create the vivado project, and provide several clocks and interrupt controller as mentioned in the tutorial here step 1, then we prepare the vitis platform with build the project in Vitis IDE as shown in this tutorial. Finally we build the project with pynq automation as directed here in dpu-pynq/boards
is my understanding correct? could anyone give me hint if any miss or wrong step?
and also I have questions. So we implement DPU as RTL kernel, is it different with implement with IP core in vivado? will it consume the logic resource? how we know how much resource that will be consumed by DPU IP core if it will consume logic fabric?
Thank you very much.