I have a very simple design that uses the AXI DMA component. The problem is that the AXI DMA send and recvchannels never go idle, so it indefinitely blocks on wait(). Here’s what I have:
import numpy as np
from pynq import Overlay, Xlnk
import time
base = Overlay('mem_pass_through.bit')
xlnk = Xlnk()
dma = base.axi_dma_0
input_buffer = xlnk.cma_array(shape=(5,), dtype=np.uint32)
# populate input buffer: [0 1 2 3 4]
for i in range(5):
input_buffer[i] = i
output_buffer = xlnk.cma_array(shape=(5,), dtype=np.uint32)
dma.sendchannel.transfer(input_buffer)
dma.recvchannel.transfer(output_buffer)
dma.sendchannel.wait() # blocks here
dma.recvchannel.wait()
print(input_buffer)
print(output_buffer)
Anybody know what could be the problem? Could it be the design itself? The design is very simple, just adds 5 to every element in the input buffer.
DMA transfers from one memory area to another. Where do you transfer your buffer to? Where from do you read to your buffer?
It looks like you wanted to use a looped FIFO
Can you post your block design as well, because the block design matters? For me, I have seen problems when connecting the interrupts coming out of DMA directly to ps irq pins (instead of relayed by the AXI interrupt controllers). Another easy way to try your code out, is to disable interrupts in your IP, and try that first without interrupts. Then if that works at least you have some confidence moving forward.
I’m not too sure, are you talking about memory locations within the FPGA? I uploaded the block design below, can you look at that and see if that answers your question? Sorry for the late response.
First, better if you disable the scatter-gather in the DMA, and I think it’s possible to disable the unused channel.
You may not need the first wait. The reason is, sending data, processing and receiving it is automated. By the time the processor executes it, the transfer may already have finished
