Thanks @cathalmccabe for your interest.
An update: I managed to achieve some progress by propagating TLAST from the Master to Slave and feeding TREADY from Slave to Master of the DMA AXI-Stream. However, I see that in the beginning of a transfer there is a burst of 4 data cycles for 32-bit wide TDATA only the first 4 data words and the last (i.e. 15th) word arrive in order where the 4th to 14th words get replaced by 15th word. Has anyone else observed this?
AXI DMA LogiCORE IP Product Guide (PG021) states “Note: In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run much before the actual data arrives.”
Is the only workaround to pad the send transfer with 16 dummy words and discard those in the received data?
How this is avoided in the AXI-DMA example?