PYNQ: PYTHON PRODUCTIVITY

Axis stream off by one

Hi im trying write my own axis driver with a minimal example and I have mostly succeeded. I have setup a minimal example with a custom ip block and some python code which streams a bunch of random numbers in. These numbers are then bitshifted by 1 bit (just as a simple example).

However for every transfer the fifth sample is always wrong. ie in my notebook (attached below) the diff array (called error) is always only zero except for the fifth sample. This is 100% reproducible(on my side). I am really puzzled by this problem.

my verilog code is here shifter2_v1_0.v (5.4 KB) and my notebook here simple-axis.ipynb (4.1 KB) Can somebody spot a problem to point me in the right direction? Thank you in advance!

The Verilog code has bugs, especially with handling tlast.

For example, say I keep tvalid and tlast asserted constantly at the slave interface. That means that every clock cycle where your code asserts tready there is a size 1 packet being transferred. Your code keeps tready constantly high, which means there is data transfer every single clock cycle.

But on the master interface, you assert tvalid only once every two cycles, that means that half the data is being lost.

I suggest debugging with a Verilog test bench first. Debugging a Verilog code that doesn’t implement the AXI-stream correctly at the Python level is hard.

Thank you for your reply. I am a little puzzled, if I were to drop 50% of my data I would have seen that in the python output no? Do you have any good recomendation of a testbench (or the best testing method) for axis streaming?

This was just the most visible problem.It seems that handling of TLAST is not done correctly in other situations as well. For example, in SLAVE_READ, when it gets a TLAST it immediately goes back to IDLE without waiting for the other site to assert TREADY.

This is simple enough that you could just write a Verilog test bench:

Just make sure you cover the interesting situations.

thank you for your reply. but late reply from me I was busy with some other projects. You have a good suggestion but my problem with writing a testbench myself is that if I made a mistake due to mis understanding the stream protocol this will also turn up in the testbench.

Are there any standard testbenches available for the most simple axis stream transfers, that you are aware of?

I’m not sure about standard testbenches, but the testbenches are usually easier to write.

You didn’t ask this, but it may help; I’d never write my own AXI interface logic as I think you did in this example.
You can generate a HDL (VHDL/Verilog) AXI interface template in Vivado, and add your HDL for the logic. I’d always use this if I needed a HDL AXI interface.

Create and Package IP wizard

If you use HLS, it will generate the AXI interfaces automatically.

There are AXI protocol checkers you can add to your design in Vivado too if you want.

Cathal