Board hangs when accessing AXI DMA from Python during RF loopback bring-up

Support
1

Hello @marioruiz ,

Kindly help me in solving the below issue

Title

PYNQ 3.1 (ZU48DR / ZCU208): Board hangs when accessing AXI DMA from Python during RF loopback bring-up

Environment

  • Board/SoC: ZU48DR RFSoC (ZCU208 class platform)

  • BSP/Image: PYNQ 3.1

  • Overlay: custom base.bit + base.hwh (contains RFDC + AXI DMA(s) + RX/TX chains)

  • Python: PYNQ notebooks (Jupyter)

What I’m trying to do

Validate an RF loopback test: DAC → (loopback) → ADC, with capture via AXI DMA to DDR and analysis in Python.

Symptoms

  • As soon as I access a DMA channel from Python (e.g., create DMA object / call sendchannel.transfer() or recvchannel.transfer()), the board hangs: Jupyter becomes unresponsive, and I must power-cycle/reboot.

  • When I simulate ADC data without DMA, all plotting/processing works fine (so user-space flow is OK).

  • RFDC control via xrfdc works (I can program mixers etc.), but DMA access causes the hang.

IP naming (from ol.ip_dict.keys() for context)

Examples:
radio/receiver/channel_00/axi_dma_0, radio/receiver/channel_00/axi_dma_1,
radio/transmitter/channel_30/axi_dma_2, … (plus RFDC tiles/blocks, decimators, spectrum analyzers, etc.)

Repro steps (high level)

  1. ol = Overlay('/run/media/base.bit') (matching base.hwh present).

  2. Create DMA handles and/or call transfers, e.g.

    • from pynq.lib.dma import DMA

    • rx = DMA(ol.ip_dict['radio/receiver/channel_00/axi_dma_0'])

    • rx.recvchannel.transfer(buf) → system becomes unresponsive.

  3. Requires board restart.

Regards,

Ashritha S

Debugging Common DMA Issues [Part 3]
2

Hi @Ashritha_S,

I moved your question to a new topic.

How did you generate the PYNQ 3.1 image?

Did you design your own overlay?

Mario

3

Hello @marioruiz
Thanks for the reply. I am not using a pre-built image or overlay. Both the PYNQ image and the FPGA overlay/design are completely custom for my platform.

My current challenge is related to DMA transfers in this custom setup.

Please let me know if you need details on the overlay design or build process.

Regards,

Ashritha S

4

We found an issue with the memory allocator that it is now fixed in the 3.1.1 branch. I suggest you rebuild the image with this branch GitHub - Xilinx/PYNQ at image_v3.1.1 or apply this patch to your pynq deployment fixing <4KB buffer allocation issue (#1500) · Xilinx/PYNQ@2ad4c72 · GitHub

5

Can u provide the python code to test RF Loopback test using DMA?

6

You will need to design your own overlay for this.

You can find plenty of examples using the DMA

7

Can u kindly share any one example of that overlay based on the DMA?

8

You can see a DMA example here: