Clickable diagram of your PYNQ overlay, with wires coloured by clock domain + CDC checks

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I made an AI skill that turns a PYNQ/Vivado project into a clickable, Vivado-style diagram, with wires coloured by clock domain.

fpga-analyzer-demo

For PYNQ overlays it also:

  • maps notebook lines (ol.axi_dma_0, dma.sendchannel.transfer) to the hardware blocks they drive
  • flags .bit/.hwh name mismatches, unknown IP names, and MMIO addresses outside the address map
  • finds unsynchronized clock-domain crossings, traced from the block design into the RTL
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Hi @Abdullah_AlNafisah

Very cool. I can imagine this being quite useful for users. Thanks for sharing.

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