PYNQ: PYTHON PRODUCTIVITY

PYNQ DMA tutorial on ZU+

Hi,
I am trying to recreate this tutorial, but with ZCU111, on Vivado 2021.1, following the instructions and steps exactly.

On using the “Run Connection Automation”, I get an address mapping error. Screengrab attached. ( showing the error notification. Cannot upload block design as only one upload is allowed for new users)

Are there steps specific to ZCU111 that must be followed? I noticed the S_AXI_HP ports on the Zynq device are labelled differently from the ones shown in the tutorial.

Thanks,
Vikas

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Adding second post to attach block design.

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Does it work when you use an AXI Interconnect instead of the AXI SmartConnect?

Hi @jancumps,

Thanks for your suggestion. I tried it, with the same result of errors and warnings. Further tried with various versions of Vivado, to no change.

The automatic connection assistance creates 3 memory networks, when it should probably be 1, as the physical memory is the same? Even it is not 1 memory network, I can imagine 2 memory networks, but don’t understand how there could be 3.

On following your suggestion, the number of memory networks can be reduced to 1, but the warnings and errors are still the same.

Perhaps I need to try and manually set the addresses. Is there a document that might help me understand how to do that?

Thanks!

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