My question might be simple, but I’m confused about how to get a referenced or expert answer. I am building an ultra-fast HLS IP that I want to test on the Kria KV260. I was wondering if my IP can achieve a 1 GHz clock speed based on the Vivado RTL implementation. What is the highest Fmax I could achieve if I want to implement it on the Kria KV260, and how challenging is it to achieve that with the PYNQ implementation? Is there any reliable reference where I can find the Fmax or the maximum clock for the PL?
This is an FPGA question, and not a PYNQ question. You may be better asking on the AMD/Xilinx forums.
The short answer is the max frequency depends on your design, and the device you are targeting. You won’t get 1GHz - this is out of spec for Ultrascale+. 200-300MHz should be possible and you may be able to go higher depending on your design. The only way you will really know is by building your design and checking the max frequency reported in Vivado.
Thank you, Cathal. Your explanation was clear, but you are right—I should have asked the first part of the question in the AMD/Xilinx forums. The second part, for example, I have a design that achieves 1 GHz after placement and routing in Vivado, and I was unsure if it would be limited by the PL clock in the ZU+ MP device or by the Pynq framework. Actually, I just used one of your tutorials, “Tutorial: AXI Master Interfaces with HLS IP”, but it was limited to 333 MHz due to the AXI interconnect and interrupt operational frequency. Therefore, it was a bit confusing that an FPGA device might support 600 MHz but be limited by interrupt configurations or the speed of DDR, or also by PYNQ framework. Therefore, why would someone manufacture such FPGA device with such high operational frequency if not reachable?
Note: my design is based only on Boolean operations and uses couple hundreds of LUTs and FFs.
