DMA sends and receives multiple times

[j_pynq]

DMA failed sends and receives multiple times

• PYNQ version & Board name & Tool Version
  KV260, Vivado 2022.1

I am following Tutorial: using a HLS stream IP with DMA (Part 2: Vivado design) to make the simple DMA project.

Since the tutorial is targeting to Z2, I modified some setting of my DMA block to make the DMA work.

I used the same source code for HLS.
The DMA block setting has small modification see PDF:

The Block design of vivado see PDF

The design ran well when you call the DMA once. When call DMA transfer again, the notebook sad the DMA is not ready. See attached PDF, look for Ipython location In [32]:

The PDF contain the screenshot for the IP block as well as the Jupiternotebook
dma_hls_tuto… (3) - JupyterLab.pdf (734.4 KB)

What I am wanting to achieve is to be able to call for DMA transfer and receieve multiple times, for example within a for loop.
Can you point out what went wrong?

[j_pynq]

Update to the issue,
The DMA wait function will never exit,

def runKernel():
    hls_ip. register_map
    dma send.transfer(input_buffer)
    print("DMA send transfer")
    dma_recv.transfer(output_buffer)
    print("DMA recv transfer")
    hls_ip.write (CONTROL_REGISTER, 0x81) # 0x81 will set bit 0
    print " set bit o）
    dma_send. wait()
    print(" send wait done")
    dma_recv.wait()
    print(" resv wait done")

[Mohammad_Hossein_Sam]

hi @j_pynq
Did you provide TLAST for the AXI DMA?

The AXI DMA needs to have the TLAST signal.
If the TLAST is not provided, you can only read the AXI DMA only once and next time it will generate the error.

Regards
Mo

[j_pynq]

Hi,
I was following Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)

My source code is based on https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp

#include "ap_axi_sdata.h"
#include "hls_stream.h"


void example(hls::stream< ap_axis<32,2,5,6> > &A,
	     hls::stream< ap_axis<32,2,5,6> > &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma hls interface s_axilite port=return

	ap_axis<32,2,5,6> tmp;
    while(1)
    {
	A.read(tmp);
	tmp.data = tmp.data.to_int() + 5;
	B.write(tmp);
     if(tmp.last)
     {
         break;
     }
    }
    

}

You can also see the TLAST signal had been sythesised

[cathalmccabe]

Check register_map (video example) before and after your transfers, to check the status of the DMA.

You can look up the details for the registers in the AXI DMA v7.1 LogiCORE IP Product Guide.

If you are sending streams of equal sizes, you need to make sure you empty the DMA each send/receive cycle. If you don’t do this, the DMA will not be idle/ready - it is waiting to finish sending data.

Cathal