DPU-PYNQ now available for ZU+ and RFSoC devices

Announcements
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We are releasing DPU-PYNQ to leverage the state-of-the-art Vitis AI and PYNQ technologies. Starting from PYNQ image v2.5 on Zynq Ultrascale boards, users can upgrade their images, install our package from PYPI, and try a few example notebooks on the board. Currently supported boards include Ultra96, ZCU104, and ZCU111. Please see our getting started guide for more details.

Some key benefits:

  1. The ability to deploy DPU designs in 6 bash command lines.

    git clone --recursive --shallow-submodules https://github.com/Xilinx/DPU-PYNQ.git
cd DPU-PYNQ/upgrade
make
pip3 install pynq-dpu
cd $PYNQ_JUPYTER_NOTEBOOKS
pynq get-notebooks pynq-dpu -p .

  2. Simple Python API to get everything ready for DNNDK run-time.

    With the pynq-dpu Python package we are releasing, users have a simple API to download the bitstream (dpu.bit) and load a DPU model (e.g. dpu_tf_yolov3.elf) during run-time.

    from pynq_dpu import DpuOverlay
overlay = DpuOverlay("dpu.bit")
overlay.load_model("dpu_tf_yolov3.elf")

    No rebooting is required, which enables quick turn-around for development.

  3. Coverage of various models using 4 example notebooks.

    With the 6 command lines mentioned before, users should be able to try the notebooks. The following DPU models are shown in the notebooks, though we definitely support more models.

    • Resnet 50 model based on Caffe framework.
    • Inception v1 model based on Caffe framework.
    • Yolo v3 model based on Tensorflow framework.
    • MNIST model based on Tensorflow framework.

  4. Demonstration of how users can train their own models on host machine.

    We show a Jupyter notebook that can run on the host side (x86 machine) so users can follow the steps to train their own models. The output of this process is a DPU model that can be used directly by the released pynq-dpu Python package.

  5. Ease of rebuilding of the DPU hardware designs.

    We have also formalized the Make flow on the host side for users to easily rebuild DPU designs. This flow can be leveraged to target different DPU configurations, or different Zynq Ultrascale boards. For more information, please check instructions on rebuilding DPU designs.

Besides these main benefits, there are a couple of other interesting features we have put into the pynq-dpu Python package. To name a few, we have pybind11 IPython magic to run C++ code in Jupyter; we have automatic AXI port width adjustment; and we have on-board compilation of deployable *.elf models into shared objects.

If you have questions, please feel free to ask them on PYNQ support forum. Finally, I hope you enjoy this piece of work made available by the PYNQ team!

The PYNQ Team

6 Likes
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By stating DPU-PYNQ is now available for Zynq Ultrascale+ does this mean another board other than PYNQ-Z1 or PYNQ-Z2 with a Zynq Ultrascale+ device on it (if yes interested about the cost of that board. Is it > £200) or you are stating that it can be interfaced to a Xilinx Zynq Ultrascale+ board?

I think is the latter because you list the 3 supported Xilinx Boards which include ZU+ devices

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Ultra96, ZCU104, and ZCU111 are officially supported, but other Zynq Ultrascale+ devices may also work if you make necessary changes - rebuilding hardware designs, getting correct DPU models, etc.

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I think you need at least vitis-ai 1.2 to get the DPU IP. Right now that DPU-PYNQ only supports zu devices since the DPU IP in vitis-ai 1.1 only support zu.

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Which versions of tools should I use? DPU-PYNQ looks like it uses Vitis 2019.2 for a bit generation, XRT 2019.2_RC2 and the Linux kernel is 2019.1 version. Are they fully compatible?

Paweł

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Yes. 2019.2 tools are compatible with 2019.1 linux kernels.

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Can I just apply the same setting and procedures of Ultra96 for a board that uses ZU3EG as the core?

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It should be fine as long as the bitstreams are compatible.

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The current version does not work with the PYNQ 2.6 image. The installation process is not reversible since it will automatically downgrade to PYNQ 2.5.1 and delete 2.6.

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We have a version supporting 2.6.0 images now.

1 Like
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Any idea how to do it on RFSOC Academia board?