PYNQ: PYTHON PRODUCTIVITY

Error: Build officical XVC project for pynq-z2 with TCL script

Hi:
I refer to here.
I’d like to build one for xvc.

Two things I’ve prepared

  • Install pynq-z2 board files for vivado 2020.2
  • Sourceode I’ve downloaded

Top tcl files test.tcl as attachment

test.tcl has been no problem until the last command:

source ${k_bd_src_dir}/bd_system.tcl

The Content of bd_system.tcl is provided by officical

I only modify here

original:

set_property -dict [ list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.preset {Microzed*} ] $processing_system7_0

Modified:

set_property -dict [ list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.preset {pynq-z2} ] $processing_system7_0

I get this error message

ERROR: [IP_Flow 19-3391] Preset pynq-z2 doesn't exist
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::add_properties -dict {CONFIG.PCW_USE_M_AXI_GP0 1 CONFIG.preset pynq-z2} /processing_system7_0"
    invoked from within
"set_property -dict [ list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.preset {pynq-z2}  ] $processing_system7_0"
    (procedure "create_root_design" line 44)
    invoked from within
"create_root_design """
    (file "../src/hw/bd//bd_system.tcl" line 203)

    while executing
"source ${k_bd_src_dir}/bd_system.tcl"
    (file "../src/hw/test.tcl" line 75)

My bd_system .tcl as attachment.

I can’t solve this problem and hope anybody help me, thanks!

My all project files in here

Building way as readme.md

2 files of attachment (test.tcl, bd_system.tcl):

  • test.tcl
# A Vivado script that demonstrates a very simple RTL-to-bitstream batch flow
#
# NOTE:  typical usage would be "vivado -mode tcl -source create_bft_batch.tcl" 
#
# ref: 
# https://forums.xilinx.com/t5/Vivado-TCL-Community/Block-Design-in-non-project-mode/td-p/484200?fbclid=IwAR0xvkp6D8eyAov6vIj1FnY_EgZTUsFCvWgkbkP7dN1944Hv_6bUjP83Z2c
#
## STEP#0:  Prepare
#
#Define output directory area
set k_output_dir "./out/" 

#clean old folder and design
exec rm -rf ${k_output_dir}            
file mkdir ${k_output_dir}

#Set project properties (create dummy(diskless) project)
set k_fpga_part "xc7z020clg400-1"
set_part ${k_fpga_part}
set_property TARGET_LANGUAGE Verilog [current_project]
set_property DEFAULT_LIB work [current_project]

#Define directory of source code and IP
set k_verilog_src_dir "../src/hw/hdl/"
set k_xdc_src_dir "../src/hw/xdc/"
set k_ip_src_dir "../src/hw/ip/"
set k_bd_src_dir "../src/hw/bd/"

#Set max-thread to build
proc num_threads_run {} {
  set k_vivado_max_core_supported 8
  set OS ${::tcl_platform(platform)}
  if { ${OS} == "Windows" } {
    set cpu_core_count [ expr ${::env(NUMBER_OF_PROCESSORS)}/2 ]
  } else {
    set cpu_core_count [ expr [exec nproc]/2 ]
  }
  if { ${cpu_core_count} > ${k_vivado_max_core_supported} } {
    set cpu_core_count  ${k_vivado_max_core_supported}
  }
  return ${cpu_core_count}
}

set_param general.maxThreads [num_threads_run]
puts "INFO: Max threads = [get_param general.maxThreads] "

## STEP#1: setup design sources and constraints
#
#Read-in verilog files from source folder
set verilog_files [ glob -nocomplain "${k_verilog_src_dir}/*.v" ]
if { ${verilog_files} != "" } {
  read_verilog ${verilog_files}
  puts "INFO: read-in verilog files: ${verilog_files}"
}

#Read-in xdc files from source folder
set xdc_files [ glob -nocomplain "${k_xdc_src_dir}/*.xdc" ]  
if { ${xdc_files} != "" } {
  read_xdc ${xdc_files}
  puts "INFO: read-in xdc files: ${xdc_files}"
}

#Read-in ip files from source folders
set ip_files [ glob -nocomplain "${k_ip_src_dir}/*/*.xci" ]  
if { ${ip_files} != "" } {
  read_ip ${ip_files}
  puts "INFO: read-in ip files: ${ip_files}"
}

#set ip repository path (not Xilinx ip, is 3rd party ip)
set_property IP_REPO_PATHS ${k_ip_src_dir} [current_fileset]
update_ip_catalog

# create the BD-Design
source ${k_bd_src_dir}/bd_system.tcl
#generate_target all [get_files .srcs/sources_1/bd/design_1/design_1.bd]
#read_vhdl -library work [ glob .srcs/sources_1/bd/design_1/hdl/design_1.vhd ]  
  • bd_system.tcl

################################################################
# This is a generated script based on design: xvc_system
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2020.2
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z010clg400-1
#    set_property BOARD_PART em.avnet.com:microzed:part0:1.0 [current_project]


# CHANGE DESIGN NAME HERE
set design_name xvc_system

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}


# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   puts "INFO: Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   puts "INFO: Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  # Create ports
  set TCK [ create_bd_port -dir O TCK ]
  set TDI [ create_bd_port -dir O TDI ]
  set TDO [ create_bd_port -dir I TDO ]
  set TMS [ create_bd_port -dir O TMS ]

  # Create instance: axi_jtag_0, and set properties
  set axi_jtag_0 [ create_bd_cell -type ip -vlnv A_Clark:Debug:axi_jtag:1.0 axi_jtag_0 ]
  set_property -dict [ list CONFIG.C_TCK_CLOCK_RATIO {16}  ] $axi_jtag_0

  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  set_property -dict [ list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.preset {pynq-z2}  ] $processing_system7_0

  # Create instance: processing_system7_0_axi_periph, and set properties
  set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ]
  set_property -dict [ list CONFIG.NUM_MI {1}  ] $processing_system7_0_axi_periph

  # Create instance: rst_processing_system7_0_100M, and set properties
  set rst_processing_system7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_100M ]

  # Create interface connections
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_jtag_0/s_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]

  # Create port connections
  connect_bd_net -net TDO_1 [get_bd_ports TDO] [get_bd_pins axi_jtag_0/TDO]
  connect_bd_net -net axi_jtag_0_TCK [get_bd_ports TCK] [get_bd_pins axi_jtag_0/TCK]
  connect_bd_net -net axi_jtag_0_TDI [get_bd_ports TDI] [get_bd_pins axi_jtag_0/TDI]
  connect_bd_net -net axi_jtag_0_TMS [get_bd_ports TMS] [get_bd_pins axi_jtag_0/TMS]
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_jtag_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk]
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in]
  connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn]
  connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_jtag_0/s_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn]

  # Create address segments
  create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_jtag_0/s_axi/reg0] SEG_axi_jtag_0_reg0
  

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""