Hello, I’m using PYNQ-Z2, Ubuntu 18.04, OpenCV 3.4.2, Vivado 2020.2 & Vitis Vision library to generate a overlay for resizing images. And I have generated the IP, using the examples in https://github.com/Xilinx/Vitis_Libraries/tree/master/vision/L1/examples/resize. The result of csim is correct, but when I’m generating the block design with the tcl script in https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/Pynq-Z2/resizer/resizer.tcl, an error occurred.
WARNING: [BD 5-232] No interface pins matched ‘get_bd_intf_pins resize_accel_0/s_axi_AXILiteS’
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] ‘connect_bd_intf_net’ failed due to earlier errors.
while executing
“connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins resize_accel_0/s_axi_AXILiteS…”
(procedure “create_root_design” line 69)
invoked from within
“create_root_design “””
(file “./resize.tcl” line 347)
update_compile_order -fileset sources_1
