I am working on a RFSOC 4*2. I have made few changes to an original Vivado design by added new IP blocks as a second Direct Memory access. I have generated the bitstream and uploaded it to the board. However, on Pynq, I am not able to see the new IP blocks created on Vivado and thus to use them. Would anyone have an idea to fix this?
Check your design and that the AXI lite interface is mapped correctly into the PS memory may.
Check you are copying the correct .bit AND corresponding .hwh to the board. (I’ve made this mistake more times than I like to admit )
If you still have a problem, please post more details about what exactly you are doing, and the code you are using to load the new Overlay.
Sorry for the late answer, the problem was indeed related to an incorrect map to the PS memory. Thank you for the help.
Can you describe in more detail how to solve your problem?