I am working on developing a kernel function in HLS. I have synthesized the IP block in HLS and I have validated it using C/RTL Co simulation. I have exported my IP. I have a small doubt. When i export my IP i can do a place and route of the IP/synthesis of the IP , in this process is the block diagram automatically created? and is the IP automatically connected via run_block automation?
When you do place and route from Vivado/Vitis HLS, it is only done for your IP. The block diagram it is not created, you need to do it manually from Vivado.
Thanks I am attaching my block diagram which uses axistream can you check if its correct?design_1.pdf (86.0 KB)
Connections look good