The Custom IP I have generated using verilog HDL is not recognized by Overlay

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1

I have created an IP of inverter for inverting image pixel value using verilog HDL for using it in PYNQ Z2 board. Then I created a block design using axi_dma and the Zynq processing system. After this i have generated an HDL wrapper, bitstream file. I have put my .bit, .hwh and .tcl files in the Jupyter lab for using the Python framework. When I am creating an overlay using a .bit file, I am getting only two IP names: axi_dma and Zynq processing system. The IP which i have generated is not coming.
Below I have attached the block design and the IP I am getting.

img_inv_blk_1.pdf (54.4 KB)

WhatsApp Image 2024-05-28 at 12.02.32_5fc73447
WhatsApp Image 2024-05-28 at 12.02.32_5fc734471280×218 41.9 KB

2

Hi @Vinit_Kumar,

Welcome to the PYNQ community.

The ip_dict only shows memory-mapped IP. Your IP only has stream interfaces and therefore does not show up in ip_dict.

Another way of understanding ip_dict is IP that can be controlled or queried from the PS. Your IP does not provide these capabilities, hence it is not part of ip_dict.

Mario