The university of Strath provided several examples. However, when I opened them in Simulink, System Generator doesn’t open!
If I delete their system generator and put the system generator from the Simulink library it opens correctly. However, when I put the right FPGA things, I face a lot of errors.
I run it with a different version of Matlab and Vivado, including the versions they suggested. This error exists for all examples.
Another issue is the path toward Matlab and then Vivado and Jupyter are unclear.
For example, if I wanna change the bit rate from 1000 to 2 Gbps, then assume passed all these difficulties make replicating their examples impossible!
Then, how updated the Vivado version of IP then how did I set up new my own design on Jupyter?
The education materials for using hardware are significantly insufficient. Also, for new people in this area, many key passes are missing.
Hi @mnaghshvarian,
I am sorry to hear that you are having issues with rebuilding the RFSoC-QPSK demonstration. I will try and help you progress as best as I can.
Can you describe the steps you are taking to open the System Generator designs? Here is a list of things I need to know:
- What operating system are you using to run System Generator?
- Are you using the correct version of Vivado and MATLAB? These should be Vivado 2020.2 and MATLAB R2020a.
- Is System Generator configured correctly? Have you executed the System Generator 2020.2 MATLAB Configurator in administrator/sudo mode and bound the tool to MATLAB R2020a?
- What specific System Generator model are you trying to open?
- Are you receiving an error when you try to open a model? What does this error report?
- Have you installed the RFSoC devices with your distribution of Vivado 2020.2?
The above should be enough to help me get started debugging your problem. Just to note, I ran tests on this repository today, and all is working as expected on our systems. At first glance, it appears you do not have something configured correctly.
Regards,
David.
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Hi David
I went through it, and actually, there are a lot
of details aren’t exactly work as mentioned in the videos. But, I was finally able to create bitstream.
I send the screenshots also. For the OFDM system, I simply like to change the fs. I just increased it to 240 MHz. Then using Matlab HDL code, I generated the HDL. However, when I compared it to other files, it was not obvious where should be copied these upgraded VHDL files (Please see attached figures). Another thing, I find out, we may not be able to increase the fs beyond the clock rate of RFSOC FPGA, could I ask you please is that true?
My other concern is our ultimate research goal is actually, is to use your example as the platform. It is ideal for us to have the symbol rate of 1 or 2 Gsym/s (Fs = 1 or 2 GHz ), then using RFonFiber, we send data on fiber optic and testify our DSP algorithms real-time based on received symbols. We developed DSP in MATLAB and would like to testify it in real-time applications. But, I’m wondering if RFSOC supports the symbol rate of ADC or not for fs (in examples, QPSK to OFDM, I find it might be an issue for random bit generation)
But, the issue, I faced, is when I want to update your examples, simply don’t know how to update it after VHDL generation.
