RFSoC 4x2 Xlinx QPSK tranceiver example

Hi! I am a senior engineering student at UC Santa Cruz and I am trying to build the project in vivado 2020.2 but am running into some issues. The make block_design command finishes with several warnings, but when I run the make bitstream command it exits with an error and I am unsure of how to fix this error. I had to download the board files directly from real digital because it would always cause an error otherwise and I don’t know if that causes any issues either. Attached is the vivado log of the session, but the issue seems to be with IP generation.

vivado.log (35.4 KB)

Are you running this from a fresh repo, or have you changed the block design in some way?

I have been working from a fresh repo each time that I try to make the design. I delete my current one and git clone a fresh copy from the repo at qpsk tranceiver

I have also uninstalled and reinstalled vivado 2020.2, the github repo and the board file which fixed the previous error and now causes a new one. The error from the log is now this one:
WARNING: [Vivado 12-8222] Failed run(s) : ‘rfsoc_qpsk_auto_cc_7_synth_1’, ‘rfsoc_qpsk_clk_rx_0_synth_1’, ‘rfsoc_qpsk_auto_cc_1_synth_1’, ‘rfsoc_qpsk_axis_data_fifo_0_0_synth_1’, ‘rfsoc_qpsk_axis_data_fifo_1_0_synth_1’, ‘rfsoc_qpsk_fir_compiler_1_0_synth_1’, ‘rfsoc_qpsk_fir_compiler_0_0_synth_1’, ‘rfsoc_qpsk_auto_ds_0_synth_1’, ‘rfsoc_qpsk_auto_pc_0_synth_1’, ‘rfsoc_qpsk_auto_cc_2_synth_1’, ‘rfsoc_qpsk_auto_cc_0_synth_1’, ‘rfsoc_qpsk_auto_cc_4_synth_1’, ‘rfsoc_qpsk_xbar_0_synth_1’, ‘rfsoc_qpsk_auto_cc_3_synth_1’, ‘rfsoc_qpsk_auto_cc_5_synth_1’, ‘rfsoc_qpsk_auto_cc_6_synth_1’, ‘rfsoc_qpsk_qpsk_rx_rrc_0_synth_1’, ‘rfsoc_qpsk_reset_256_0_synth_1’, ‘rfsoc_qpsk_reset_128_0_synth_1’, ‘rfsoc_qpsk_reset_pl_0_synth_1’, ‘rfsoc_qpsk_axi_smc_1_0_synth_1’, ‘rfsoc_qpsk_clk_tx_0_synth_1’, ‘rfsoc_qpsk_smartconnect_0_0_synth_1’, ‘rfsoc_qpsk_dma_tx_fft_0_synth_1’, ‘rfsoc_qpsk_dma_tx_symbol_0_synth_1’, ‘rfsoc_qpsk_dma_rx_csync_0_synth_1’, ‘rfsoc_qpsk_dma_rx_dec_0_synth_1’, ‘rfsoc_qpsk_qpsk_rx_csync_0_synth_1’, ‘rfsoc_qpsk_dma_rx_rrc_0_synth_1’, ‘rfsoc_qpsk_qpsk_rx_dec_0_synth_1’, ‘rfsoc_qpsk_qpsk_rx_tsync_0_synth_1’, ‘rfsoc_qpsk_dma_rx_tsync_0_synth_1’, ‘rfsoc_qpsk_zynq_ultra_ps_e_0_0_synth_1’, ‘rfsoc_qpsk_usp_rf_data_converter_0_0_synth_1’, ‘rfsoc_qpsk_reset_25_6_0_synth_1’, ‘rfsoc_qpsk_reset_pl_1_synth_1’, ‘rfsoc_qpsk_rst_ps8_0_99M_0_synth_1’, ‘rfsoc_qpsk_auto_cc_9_synth_1’, ‘rfsoc_qpsk_axis_data_fifo_1_1_synth_1’, ‘rfsoc_qpsk_reset_128_1_synth_1’, ‘rfsoc_qpsk_fir_compiler_0_1_synth_1’, ‘rfsoc_qpsk_auto_pc_1_synth_1’, ‘rfsoc_qpsk_auto_cc_8_synth_1’, ‘rfsoc_qpsk_axis_signal_join_0_0_synth_1’, ‘rfsoc_qpsk_dma_tx_time_0_synth_1’, ‘rfsoc_qpsk_xbar_1_synth_1’, ‘rfsoc_qpsk_auto_ds_1_synth_1’, ‘rfsoc_qpsk_auto_cc_10_synth_1’
wait_on_run: Time (s): cpu = 00:00:06 ; elapsed = 00:04:10 . Memory (MB): peak = 1849.805 ; gain = 0.000
error copying “./block_design/block_design.runs/impl_1/rfsoc_qpsk_wrapper.bit”: no such file or directory
while executing
“file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${design_name}.bit”
(file “make_bitstream.tcl” line 20)

I just tried to build the design myself and it worked with no issues. There’s a few things you might need to try:

  • The Makefiles are designed for use in Linux. Are you using an appropriate Linux distro to build this?
  • Make sure you’re using Vivado 2020.2 and it’s available on your path. Running echo $PATH in your terminal should show that the Vivado tools are available.
  • Make sure the RFSoC4x2 board files are in the correct location. On Vivado 2020.2 I think these are in /tools/Xilinx/Vivado/2020.2/data/boards/board_files or something similar. Alternatively, you can add set_param board.repoPaths <path/to/board/files>​ to the boards/RFSoC4x2/rfsoc_qpsk/make_block_design.tcl file on line 5 (above the create_project line.
  • Make sure you have the appropriate license for building for RFSoC devices.

Interesting, I did not realize the system needed a Linux distro to build it. I have been trying to run the makefile for the block design and bitstream through Vivado 2020.2 itself. I was thinking my problem was that I did not do the system generator for dsp step first before trying to do vivado. I have the board files in the right location as well as a path to it being set up. I am not sure if I have the appropriate license for building RFSoC because I am using a university license. What steps did you take to build the design and how would I go about using a Linux distro to build it?

You can build the design on Windows, but the Makefiles expect your OS to be Linux.

To build on Windows, open Vivado and navigate to the repo in the tcl console using cd.

  • cd <path/to/repo>/boards/RFSoC4x2/rfsoc_qpsk/
  • Make sure the board files are on your path using set_param board.repoPaths <path/to/board/files>
  • Then run source make_block_design.tcl
  • Once the block design has been built you can generate the bitstream using the Vivado GUI.

Hope this helps.


1 Like

Thanks for the reply. From you information I found out we did not have the correct license and have since fixed that. Now after running the system generator files to generate some IP I am running into a different error. When writing the bitstream it is now giving this error:

  • [Vivado 12-7073] file C:/Capstone/rfsoc_radio/boards/RFSoC4x2/rfsoc_radio/block_design/block_design.runs/rfsoc_radio_auto_cc_2_synth_1/rfsoc_radio_auto_cc_2.dcp already exists and is not writable.