PYNQ: PYTHON PRODUCTIVITY

HLS synthesis fails due to error: too many template arguments for class template 'stream'

I am currently learning how to use the HLS Design flow works. For that I’ve followed the provided example from this GitHub Page: https://github.com/Xilinx/PYNQ-HelloWorld/tree/master/boards/ip/hls

But during the synthesis I bump into this error.

in file included from ../vitis_lib/vision/L1/include/common/xf_common.hpp:20:
../vitis_lib/vision/L1/include/common/xf_structs.hpp:436:10: error: too many template arguments for class template 'stream'
    hls::stream<DATATYPE, XFCVDEPTH> data;

My best guess is that I probably miss some packages that I need during the synthesis.
I really want to understand it but I don’t have any experience with HLS or C++.
I’ve tried to rebuild the IP in an Ubuntu 16.04.6 VM and Vivado 2019.2 and tried to build it in Windows 10 Vivado 2019.2. Both failed with the same error.

I already posted the question on GitHub and on the Xilinx Forum but unfortunately didn’t get an answer. I hope this question is not too stupid… :confused:

Thank you very much in advance! :relaxed:

C_Synthesis.log (5.8 KB)
resize_accel_csim.log (13.3 KB)

I need to know what exactly you did. Did you just go to resize folder and run make? I think I have tested that and it worked fine.

Hey @rock thank you very much answering me! :relaxed:
I am sorry that I didn’t make msyself clearer. :pensive:

And yes I’ve just run the make command. I’ve also cloned the Vitis Libraries Repository and named it “vitis_lib”. In the Vitis Libraries Repository I’ve also checked if they had done changes on the code that might causes the error, but the last change was 9 months ago. So I think that couldn’t cause the error.

I saw in the make file that it calls the Vivado HLS. It is my first time using HLS, so I didn’t configure anything or installed additional packages.

Do you need to install some packages or need to run a certain setup before using Vivado HLS?
Or any other clue what I might doing wrong?

Thank you very much for helping me!!

I think you should just do:

git clone --recursive https://github.com/Xilinx/PYNQ-HelloWorld.git

Then the IP is ready to be built inside boards/ip/hls/resize. Run make there.

1 Like

It workd @rock :heart_eyes: :heart_eyes: :heart_eyes:
You are really awesome :scream:

I am soo thankful. I struggled soo much and searched for quite a long time to figure out a solution. :sob:

I would have never imagened that manually cloning the Vitis Libraries Repository and name it manually “vitis_lib” would through such a weird error.
And I also didn’t know that git clone --recursive would also clone the linked repositorys!

I hope this post is also relevant for other people who want to try to rebuild the resize ip :relaxed:

Just for my own curiosity:
Do you have any idea, why this strange error occured? Because even if I manually git clone the vitis libraries repository why should it throw such a weird error in the HLS synthesis?