M_axi write & read not working


I am trying to get an hls design to run on hardware but it is not working as intended at all.
I tested out various syntaxes and also tried simplified the design to just see if it works and also to check if the bit stream generated from Vivado is correct - IT WORKS, also CSim works (effortlessly).

But the moment I add the actual code, it just doesn’t. I have attached the top function and the sub functions in a single file, a pic of the block design (as I mentioned, it works for a simplified design, so probably nothing wrong here), pynq code.

Vivado and Vitis versions - 2023.2
Hardware: Kria SOM 260

The trouble is, output_buffer1 is not getting all the values from the 2nd and 3rd iteration.

Is there a way to debug the hls code stepping line by line? Preferably with Pynq?

Thanks in advance. It would be of immense help.

looks like having DATAFLOW within the sub-function merge_sort_top prevents iterations 1 and 2 from executing. If I comment it (dataflow pragma) out, it works, But then, if I comment it out, then I have to provide depth for the hls::stream which would then limit again how much data I can process. Thus stuck again.

I’d have to get dataflow working within the sub-function merge_sort_top, that is the challenge now.

top_src_latest_not_working_backup.cpp (10.1 KB)
dma_hls_tutorial (1).ipynb (275.3 KB)

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