I read and retry servel tips in how to use axi in pynq. It use the FIR IP with DMA. However, If we use a self define AXI interface IP, how could we achieved it in our way.
Currently i only have experience doing it in HLS, in these 3 videos you can learn how to use it using HLS.
It’s fairly straightforward.
There is also a possibility to define AXI IPs using vivado but I don’t know how yet.
To get quick results, it’s probably best to write a bridging IP in HLS to handle communication with the AXI bus, and connect it to your VHDL/verilog modules. It’s stupid but it will work, I think.
Best of luck
Take, a look:
I have created a design that uses: M-AXI, AXI-lite, DMA
You could take a look
M-AXI for 2d arrays you could use MAT-MUL example in Vitis for pointer only solution.
If you want to do this in Verilog I did a few tutorials on this in the Learn area: