How to implement a pipelined design monitored and controlled by PYNQ?

– PYNQ version 3.0.1, ZCU208

For my research I need to build a high-data-rate pipeline that runs independently of the SoC. However, I would like to be able to access data in the pipeline and control some memory-mapped registers that influence the data as it passes through the fabric (changing offsets or multipliers, modulation, etc.). However, all the examples given in the tutorials are sort of on-request things: data is read and sent only when Python writes commands to the various IP blocks in a design.

Here’s highly-simplified version of what I have in mind. The Stream_Processor IP is a simple AXI-Stream feedthrough that delays the signals for one clock cycle, during which the TDATA is multiplied by the value stored in one register and the value stored in another register is added to it. There is also a port that, at a slower data rate, should at some point feed a RAM buffer via AXI-Stream to a DMA core, but I’ll figure out how to do that when the rest of this works…
rfdcpo_simple.pdf (92.5 KB)
Here’s a screengrab of the simulation of my IP. The first two indices of the registers are gain and offset, and the third is the result. The registers are set and read over AXI, and there’s internal code to ensure that the first two are only written to, and the latter two are only read from.

In any event, I am feeding the correct ADC channel with a signal (tested using one of the RFDC tutorial notebooks), but try as I might I can’t figure out how to get this data to stream through to the DAC.

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Hi @redson

I believe you need the AXI Data Mover

This IP Core differs from the AXI DMA in that it allows you to issue commands using an AXI4-Stream interface rather than using AXI4 registers (from the PS). Have a look and see what you think. I have used this before, but I don’t have any work I can make public. It works very well.


Thanks David, I’ll take a look first thing tomorrow morning. Is there a reason why you can’t connect the ADC AXIS to the DAC AXIS (optionally through an AXIS FIFO or any other AXIS IP) and get the same signal out that you put in?