Implementation of Vitis IP in Vivado and creation of Bitstream

Support
1

Hello everyone,
I’ve just started learning how to use Xilinx products. I have created a simple IP to calculate a function on the image.
"#include

float calculer_tension(float resistance, float intensite) {
float tension;
tension = resistance * intensite;
return tension;
}

int main() {
float resistance, intensite, tension;

std::cout << "Entrez la valeur de la résistance (en ohms) : ";
std::cin >> resistance;

std::cout << "Entrez la valeur de l'intensité (en ampères) : ";
std::cin >> intensite;

tension = calculer_tension(resistance, intensite);

std::cout << "La tension est de " << tension << " volts.\n";

return 0;

}"

I obtained the IP that I integrated into Vivado. I want feedback on the LED_PORT. I get an error after generating the Bitstream as shown in the image. Can you help me fix this please?

[DRC UCIO-1] Unconstrained Logical Port: 32 out of 162 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: LED_PORT[31:0].

22
221650×1275 87.1 KB

Thanks

1 Like
2

This isn’t a PYNQ question. You should post questions like this to the Xilinx forums

You need to specify pin constraints for the LED port. You need an XDC file with the constraints, or you can go to IO planning in Vivado and enter constraints in the GUI.

Cathal

1 Like
3

Thanks You i fixed it.
Now in pynq jupyter notebook, when I imported the IP. Im getting this error: <<TypeError: ‘AddDriver’ object is not callable>>.
Please how can I fixed it according those files?
Thanks
ohms.zip (56.5 KB)

4

Hi @akouete25,

From the code you provide:

ohms = ol.ohms_0
...
tension = ohms(resistance, intensite)

ohms is not callable, you need to call its methods. Based on the Driver you wrote, you should do tension = ohms.add(resistance, intensite)

You can check an example here

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/overlay_tutorial.html#Creating-a-Driver

Mario

5

Thanks@marioruiz
I fixed it.
I’m getting 0.00 as the result when I was supposed to receive 20.00.
Image in attachment.
Can you help me please?

ohms
ohms1418×786 42.4 KB

Thanks

1 Like
6

Have you verified your IP in simulation?

7

You mean in Pynq Jupyter nootbook or Vivado or Vitis HLS?

8

In Vitis my code is like this.

HLS
HLS828×638 27.9 KB

1 Like
9

Hello,
Have you seen my C++ code in Vitis?