Pynq-Z2 problem creating base.bit from source/base.tcl

Support
1

I am trying to build base.bit under windows 10 and vivado 2020.2 using source ./base.tcl but it fails at implementation. The end of the runme.log file contains the following:
"Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12e6c6fce

Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 3543.016 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 12e6c6fce

Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 3543.016 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: ‘IO Clock Placer failed’
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: ca0a112b

Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 3543.016 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
162 Infos, 174 Warnings, 22 Critical Warnings and 5 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Wed May 8 16:47:31 2024…"

Thanks any feedback would be useful

Tony

2

Did you make any changes to the base.tcl?
Did you include the XDC file or other constraints in your design?

Are there other warnings or errors related to constraints?

Cathal

3

I did not make any changes to base.tcl or base.xdc but after looking for errors / warnings it seems that the originally supplied base.xdc in the PYNQ-MASTER had the following:

LEDs

set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {LED}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {RESET_DEBUG}]
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {leds_4bits_tri_o[2]}]
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {leds_4bits_tri_o[3]}]
Correcting this has allowed it to build the bitstream.

Many thanks for your helpful insight to where the problem lay.

4

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