Loops when writing code for PYNQ

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1

I am curious as to the looping convention when writing HLS:

L1:...
    L2:...
        L3:...

Why is this done?

E.g: Vitis_Accel_Examples/adder.cpp at 53e7d4fd8e1a8a431b53aff47dfcb6c5d19d9686 · Xilinx/Vitis_Accel_Examples · GitHub

2

Why the loops are labelled? This can be useful for identifying a loop when applying HLS optimizations, or understanding how the design has been optimized.

If you are using pragmas, they can be inlined with the loop. Labels are less important.
However, optimizations can also be applied using Tcl commands which are separate to your code. The optimization needs a way to identify the code or loop in this case.

E.g.
From here:
https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/set_directive_loop_tripcount

set_directive_loop_tripcount -min 12 -max 16 -avg 14 foo/loop_1

directive is applied to the loop labelled “loop_1” in fn foo

Cathal

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