Thank you, Cathal. Your explanation was clear, but you are right—I should have asked the first part of the question in the AMD/Xilinx forums. The second part, for example, I have a design that achieves 1 GHz after placement and routing in Vivado, and I was unsure if it would be limited by the PL clock in the ZU+ MP device or by the Pynq framework. Actually, I just used one of your tutorials, “Tutorial: AXI Master Interfaces with HLS IP”, but it was limited to 333 MHz due to the AXI interconnect and interrupt operational frequency. Therefore, it was a bit confusing that an FPGA device might support 600 MHz but be limited by interrupt configurations or the speed of DDR, or also by PYNQ framework. Therefore, why would someone manufacture such FPGA device with such high operational frequency if not reachable?
Note: my design is based only on Boolean operations and uses couple hundreds of LUTs and FFs.
Thank you
Majed