Multiple DMA: stall!

[marioruiz]

Hi @alienflip,

Welcome to our community. As you are using the tools 2022.1, the HLS compiler is Vitis HLS not Vivado HLS.

Vitis HLS does not generate AXI4-Stream from structure properly. To generate AXI4-Stream interfaces you need to use something like this hls::stream< ap_axis<32,0,0,0>.

You can review Cathal’s tutorial for more information.

Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)

Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design) In a previous tutorial I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, part 2 shows how to build the Vivad…

Mario