I am currently working on the rfsoc offload exemple(GitHub - strath-sdr/rfsoc_qsfp_offload: RFSoC QSFP Data Offload Design with GNU Radio) and I made some modifications to the Vivado design in order to use the 2 DAC available on the RFSOC 4*2 (so I added another DMA, another FIFO controller, enabled the second DAC (tile 230)…). I managed to succesfully generate the bitstream.
Moreover, on PYNQ I modified the “.bit” file in the Overlay class in order to use the one corresponding to the modifications I made on Vivado. However, when I check the IP hierearchy (by running the ip_dict command), I don’t see the new IP blocks that I have added on Vivado. So, I don’t have access for instance to the second DMA I have created on Vivado.
Would you know why and where is it coming from?
Thank you in advance,
If you changed the IPI block design you will need both the new .bit file and the .hwh file. If you used the Makefile within the
boards/RFSoC4x2 directory to build the design, this should automatically copy the .hwh file into the
bitstream directory. If you rebuilt the design in Vivado you will have to copy this file manually. It should be located in
Hi, Thank you for your answer, now it works. However, when I want to use the second DMA on pynq, it gets stuck( whereas the first one works well). Would you have any idea what can be the problem?
The DMA is a sticking point for a lot of people. I’d suggest looking through the forum for other posts regarding this matter and see if any of the solutions work for you. The usual culprit is the AXI-Stream tlast signal not triggering at the correct time. If you can’t find an answer I’d suggest making a new forum post and we can look at it in more detail.
Thank you for your asnwers. The problem is resolved now so it is all set.