PYNQ: PYTHON PRODUCTIVITY

Multiple DMAs, But only one work

Hi everyone,
I created a Block Design on Vivado 2018.3 where I used the DMA to transfer data from memory to AXI Stream Data FIFO IP block and back to the memory.There are two DMA IP block,and I connected AXI_DMA0 to AXI_HP0 and AXI_DMA1 to AXI_HP1.Then I generated the bitstream file.
But finally, I found that only one of the DMAs can work properly. I don’t know why?
Thanks in advance

Python code I’m running:

The error: