Multiple DMAs, But only one work

Support
1

Hi everyone,
I created a Block Design on Vivado 2018.3 where I used the DMA to transfer data from memory to AXI Stream Data FIFO IP block and back to the memory.There are two DMA IP block,and I connected AXI_DMA0 to AXI_HP0 and AXI_DMA1 to AXI_HP1.Then I generated the bitstream file.
But finally, I found that only one of the DMAs can work properly. I don’t know why?
Thanks in advance

1
11609×715 81.4 KB

1 Like
2

22
22726×377 13.7 KB

3

Python code I’m running:

33
33677×704 9.17 KB

4

The error:

434
434541×598 19.2 KB

1 Like
6

I have same issue … Any solution to this anyone?

7

@Animesh_Pareek please don’t respond to old posts (3 years old).
Please open a new post with details of your problem.

Cathal