Partial reconfigure problem with pynqv2.7

Support
1

-PYNQv2.7, pynq z2, vivado hls 2020.1 and vivado 2020.1

  • I uesd simple ip core to test partial reconfiguration.
    void add(int a, int b, int& c) {
    #pragma HLS INTERFACE ap_ctrl_none port=return
    #pragma HLS INTERFACE s_axilite port=a
    #pragma HLS INTERFACE s_axilite port=b
    #pragma HLS INTERFACE s_axilite port=c

c = a + b;
}

image
image1472×684 111 KB

but when I ran in jupyter notebook
ip = overlay.hier_0.add_0
ip.write(0x18, 6)
the board will hang out. I am sure the offset is right.

2

Hi @luwawa,

Welcome to the PYNQ community.

There is a small bug when handling PR in pynq. To address this, the base address inside of the reconfigurable module should be 0. Or, you can update the Python code not to (re)use the offset inside of the RM.

You can change this line

to

merged_ip_dict[ip_name]['phys_addr'] = self._ip_dict[parent]['phys_addr']

This bug will be solved in the next release.

Mario

3

Hi marioruiz,

Thank you for your answer! I have a few related questions.

1.ip = overlay.hier_0.add_0
ip.write(0x18, 6)

and

IP_BASE_ADDRESS = 0x40000000
ADDRESS_RANGE = 0x1000
ADDRESS_OFFSET = 0x10
mmio = MMIO(IP_BASE_ADDRESS, ADDRESS_RANGE)
data = 0xdeadbeef
self.mmio.write(ADDRESS_OFFSET, data)
result = self.mmio.read(ADDRESS_OFFSET)

These two methods are actually the same. Is that correct?
2. In another case, I create an IP core that has axi control signal(offset is 0x00).
ip = overlay.test
ip.write(0x00, 0x1)
isready = ip.read(0x00)
while (isready == 1): # wait PL to finish
isready = ip.read(0x00)

I use this way to start the core. But when I use mmio way(mmio.read(0x00), the control signal will never change. Do you know why this happen?
Thank you very much!

4

Hi,

The DefaultIP gets assigned an MMIO object with the proper base address and range.

For question 1, why are you using self.?
These two methods are the same yes.

For 2, it is likely that the base address for the mmio object is not correct.

Mario

5

Hi,

Thank you for your reply!

For 1, I mistype. Sorry for that.

For 2, I got correct result in this way(ip = overlay.test), so I think block design is correct. For base address, should I use 0x43C00000? When I use this address, reading 0x00 and it will never change.

image
image945×216 12.3 KB

Do you think there are other potential reasons?

Thanks!

1 Like
6

Yes, that’s the correct address.
Did you start the IP? What are you doing before reading from register 0?

7

In this question, vivado doesn’t generate register information for partial reconfiguration. So can I use mmio.read and mmio.write to replace method(
ip.s_axi_CTRL.register_map.xxx) without register information in .hwh file?
Thanks!

8

Yes, you can.

You can also add the register information yourself as indicated in my last comment in that topic.

Mario