Partial reconfiguration - PYNQ Z1

[tsand]

I am having using partial reconfiguration for a PYNQ-Z1 board.

I have been trying to replicate the example in this thread:

Dma channel not started when partial reconfig

Hi All, A simple dma design is in use. Adding two dma stream input(dma_in1, dma_in2) and stream output(dma_out). Add is by HLS IP. [image] disable scatter gather engine and all the other settings as default enable axi HP0 slave port [image] [image] [image] [image] What I want do is just add/sub for partial reconfiguration. Before downloading partial bitstream , I used API channel.idle and found dma is not in idle, but still continue to download add partial bitstream and error message…

But I am running into an issue on how this person got addsubpr_0 as a partition region.

My block diagram looks like this initially (first picture)

and then I create a hierarchy block containing add_0 and sub_0 and name it addsubpr_0. I get an error when I try to make addsubpr_0 a partition definition. The error says: ERROR: [Vivado 12-4865] Failed to create reconfig module as Block Designs type module cannot be made into reconfigurable module

I do not understand how if you’re going to use pr.download() in jupyter notebook if you cannot use a hierarchy block for a partial definition.