I am having an issue with partial reconfiguration

full configurations are working fine but I am having Problem with Partial reconfiguration.
Bitstreams.zip (7.0 MB)
This is full and partial bitstreams and hwh file is also attached
This is board design file


Source_code of pynq
source_code.ipynb (228.5 KB)

This is the error i am getting

whenever I apply full bitstreams dma works fine and gives output

Also I am sending 2 matrix through dma and receiving another matrix

This is the output when I am doing full configuration

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Can you please print the register map of the axi dma before recv_channel.transfer(output_buffer_test) and after it, but before recv_channel.wait()?

Did you check this tutorial?

Debugging Common DMA Issues [Part 3]

Hi @Shivkant_IIITD,

Welcome to the PYNQ community. You should provide information about the board, PYNQ and Vivado version you’re using.

Is desing_blank the partial region? I don’t see you using DFX decouplers, this sometimes is necessary to make sure the signals don’t float.

Mario

I am using viavdo 2019.1 version and pynq Z2 board is used in this design . No design is not blank . Also I am new to DFX I dont know how to use dfx decouplers

It is unclear which part you would like to use for partial reconfiguration. I would suggest you use a newer Vivado version, for instance 2022.1 which is supported in PYNQ 3.0.1.

Also, I suggest you read the DFX documentation and DFX example in the Vivado documentation.

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Earlier board design wasnt correct this one is correct one


Also STA_TRFI is partial region