Partial reconfigure problem with vector add

-pynq v2.7 pynq z2 vitis_hls 2020.2 vivado 2020.2

  • I use HLS to generate IP core

#include “ap_int.h”
#include “ap_fixed.h”
#include “hls_math.h”

int test(ap_int<64> a[3], ap_int<64> b[3], ap_int<64> c[3])
#pragma HLS INTERFACE m_axi port=a offset=slave bundle=data0
#pragma HLS INTERFACE s_axilite register port=a bundle=ctrl
#pragma HLS INTERFACE m_axi port=b offset=slave bundle=data1
#pragma HLS INTERFACE s_axilite register port=b bundle=ctrl
#pragma HLS INTERFACE m_axi port=c offset=slave bundle=data2
#pragma HLS INTERFACE s_axilite register port=c bundle=ctrl
#pragma HLS INTERFACE s_axilite register port=return bundle=ctrl
for (int i_chaining_0 = 0; i_chaining_0 < 3; i_chaining_0 += 1)
c[i_chaining_0] = a[i_chaining_0] + b[i_chaining_0];

return 0;
All work fine with the full bitstream. I just create a hier block and create partial definition in vivado. I program the FPGA with a partial bitstream the accelerator becomes unresponsive (ap_start stays at 1 and there is no output).
ip = overlay.test
ip.write(0x00, 0x1)
isready =
while (isready == 1): # wait PL to finish
isready =
isready is always 1. My situation is similar to this question, but no one answer yet.


Have you included a DFX AXI Shutdown Manager in the AXI4 interfaces? If so, are you controlling it while downloading the partial bitstream?

The Dynamic Function eXchange (DFX) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition and the static logic safe during dynamic reconfiguration. When active, AXI transactions sent to the Reconfigurable Module (RM), and AXI transactions emanating from the RM, are terminated because the RM might not be able to complete them. Failure to complete could cause system deadlock. When inactive, transactions are passed unaltered.


Hi Marioruiz,

Thank you for your reply!!!

I use a dfx decoupler. Is that enough? This is my design.

My code:

pr = overlay.dfx_decoupler_0
pr.write(0x00, 0)
pr.write(0x00, 1)
overlay.pr_download(‘hier_0’, ‘partial.bit’)
pr.write(0x00, 0)
ip = overlay.hier_0.test_0

But it doesn’t work.

And for dfx axi shutdown manager, if I use that IP core, should I also include a dfx controller? And how do I control that IP in pynq?(just read and write the control register of the dfx controler?) Thank you very much!

The dfx axi shutdown manager is for the AXI4MM interfaces (the ones the right of your IP) not for the AXI4-Lite.

For the AXI4-Lite you need the DFX decoupler.

You can see how we control the dfx axi shutdown manager on PYNQ here.

Hi Marioruiz,

Thank you for your reply!

Do you mean that for s_axi_ctrl port, I need to use dfx decoupler, and for m_axi_data(0,1,2) ports, I need to use dfx axi shutdown manager?

Yes. That’s what I meant

Do you have any example design using DFX AXI shutdown manager? Thanks!

And I tested it. Is that the case?

I write 0x00 to 1 before download partial bitstream and write 0x00 to 0 after I download partial bitstream.

We use the DFX AXI Shutdown manager in all of our base overlays, but not for partial reconfiguration. The code we use to control it is in one of my comments above.

We do not have an example of this with partial reconfiguration.

What problems are you having?

I added 3 shutdown managers for the three data ports.

ip = overlay.test
ip.write(0x00, 0x1)
isready =
while (isready == 1): # wait PL to finish
isready =

isready is always 1. Nothing has changed.

You don’t mention if you are controlling the shutdown manager when downloading the partial bitstream.

Regardless, you may need to do low level debugging with an ILA.

I am afraid that this topic (DFX with external memory) is quite advanced for this forum.

You may be better off asking in the Xilinx forums.


I try to control but I am not sure if it is correct. (I write 0x00 to 1 before download partial bitstream for shutdown manager and write 0x00 to 0 after I download partial bitstream for shutdown manager.)

Thanks, I will also try to ask in the Xilinx forums.

Yo have slightly more information in the register in offset 0x4. Perhaps that can help you.

Do you mean for the DFX AXI shutdown manager?


Could you give me a hint about what is in 0x04. I changed hw design a little(switch dfx decoupler to dfx shutdown manager) and tried today and I just read 0x04. It is 0 or 15. now the program will not stay in while loop but results are wrong ( always 0)

Apologies, I misread the product guide. The status register is mapped to the same register as the control one

Does pynq support partial bitstream generated by the way of block design container now?

This had been asked by me days ago:

Or I extend a bit why I had asked these questions before even start cont’d PYNQ implementations.
The supporting ground of PYNQ is critical for designer or engineer to know what we can do or we cannot do on PYNQ 2.7 2020.2.

Meantime, don’t even confused by the Composable Overlays concepts!

hi marior,

does composable overlay hardware design(.xpr) open source?

I got it. Thank you for your reply. Have you succeeded in dfx using pynq? Have you met the same problem?