Sorry it took so long to get back to you.
At present the PYNQ framework will only consider the IOPLL when setting a clock frequency and for the Ultra96 standard design this is set to 1500 MHz meaning that only divisions of 1500 will get set correctly. It also won’t try to reconfigure PLLs has that can have broader system implications.
The easiest way to get a 200 MHz clock reliably is to add a clock wizard in the fabric and generate a new 200 MHz clock from the default fabric clock of 100 MHz.
Supporting other PLL settings is something we can look into in the future.
Out of interest, did you recreate a BOOT.BIN or otherwise force the clocks to 200 MHz prior to loading the bitstream?
Peter