What I want do is just add/sub for partial reconfiguration.
Before downloading partial bitstream , I used API channel.idle and found dma is not in idle, but still continue to download add partial bitstream and error message pop out
The program stuck on dma_out channel.
my environment:
PYNQv2.5
HLS2019.1
Vivado2019.1
By the way, if i just use add hlsip to perform add function in full configuration, it worked.
Thanks for everyone’s help.
From the block design you provided, I cannot see the partial reconfiguration region. AFAIK, partial region has to be on a hierarchical block, not an IP. I don’t see how you did that.
First, addip synthesize and then subip.
Second, draw pblock on cell sub region
Third, set HD.RECONFIGURABLE 1 on cell sub
Forth, implement design and save
Sixth, remove sub cell by command update_design -cell sub -black_box
Seven, lock design
Eighth, read add checkpoint to cell and then implement again
After pr_verify between sub & add, and generate bitstream
Just follow step and type tcl command .
Perhaps i made some mistakes in some steps. But i don’t know where
Where can i find hierarchical block design tutorial? i can try it.
Thanks for your reply and help.
Hi @rock,
Thanks for your answer. After that, I searched keyword “partial reconfiguration” on youtube, and found one video titled “Partial Reconfiguration on Vivado 2018.3 with PYNQ:Partial Reconfiguration on Vivado 2018.3 with PYNQ - YouTube”. I referred to github example provided by author. In the meaning time, i changed my design to be more simple . Now, i just test add/sub function. it just use two axilite ports
they are in hierarchy block.
I test on jupyter_notebook and found a strange phenomenon. After downloading full bitstream, i test add function and sub function. It worked!!! However, add and sub partial bitstream don’t download yet.
The full bitstream will contain your default partial bitstreams; so even only after you download the full bitstream, the design will still work since your partial region is loaded with the default partial bitstreams.
Also, I just noticed that you used your own python codes to load the bitstream, can you please just use our overlay class to download overlay - it will make sure a few other things are working properly - e.g. clock, ip_dict, etc. The examples can be found at bycul repo as you mentioned. You should be able to load partial bitstreams by just 1 or 2 lines.
The youtube video has a small issue - it would be safer to add the PR decoupler.
