PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Dma channel not started when partial reconfig

Hi All,
A simple dma design is in use. Adding two dma stream input(dma_in1, dma_in2) and stream output(dma_out). Add is by HLS IP.


disable scatter gather engine and all the other settings as default
enable axi HP0 slave port



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What I want do is just add/sub for partial reconfiguration.
Before downloading partial bitstream , I used API channel.idle and found dma is not in idle, but still continue to download add partial bitstream and error message pop out

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The program stuck on dma_out channel.
my environment:
PYNQv2.5
HLS2019.1
Vivado2019.1
By the way, if i just use add hlsip to perform add function in full configuration, it worked.
Thanks for everyone’s help.

From the block design you provided, I cannot see the partial reconfiguration region. AFAIK, partial region has to be on a hierarchical block, not an IP. I don’t see how you did that.

Hi,
i refer chapter 3 vivado software flow in ug909: vivado partial reconfiguration.pdf


First, addip synthesize and then subip.
Second, draw pblock on cell sub region
Third, set HD.RECONFIGURABLE 1 on cell sub
Forth, implement design and save
Sixth, remove sub cell by command update_design -cell sub -black_box
Seven, lock design
Eighth, read add checkpoint to cell and then implement again
After pr_verify between sub & add, and generate bitstream
Just follow step and type tcl command .
Perhaps i made some mistakes in some steps. But i don’t know where
Where can i find hierarchical block design tutorial? i can try it.
Thanks for your reply and help. :yum:

Hi @rock,
Thanks for your answer. After that, I searched keyword “partial reconfiguration” on youtube, and found one video titled “Partial Reconfiguration on Vivado 2018.3 with PYNQ:https://www.youtube.com/watch?v=sgjPbaguWCg&t=721s”. I referred to github example provided by author. In the meaning time, i changed my design to be more simple . Now, i just test add/sub function. it just use two axilite ports
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they are in hierarchy block.
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I test on jupyter_notebook and found a strange phenomenon. After downloading full bitstream, i test add function and sub function. It worked!!! However, add and sub partial bitstream don’t download yet.

The red circle just show the correct value. At that moment, just full bitstream downloaded.

Did I do something wrong during generating bitstream process?
Did full bitstream have partial bitstream function?

Thanks for your kindly help :blush:

The full bitstream will contain your default partial bitstreams; so even only after you download the full bitstream, the design will still work since your partial region is loaded with the default partial bitstreams.

Also, I just noticed that you used your own python codes to load the bitstream, can you please just use our overlay class to download overlay - it will make sure a few other things are working properly - e.g. clock, ip_dict, etc. The examples can be found at bycul repo as you mentioned. You should be able to load partial bitstreams by just 1 or 2 lines.

The youtube video has a small issue - it would be safer to add the PR decoupler.

Hi @rock,
Thanks for your reply. You are right. Based on my experiment, PR decoupler is a must when performing partial reconfig.


Big thanks for your reminder.