AXI TCAM Wrapper (Couldn’t upload this due to limitations on a new user , sorry for the trouble)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.01.2025 14:30:38
// Design Name:
// Module Name: axi4_tcam_wrapper
// Project Name:
// Target Devices:
// Tool Versions:
// Description: AXI4-Lite interface wrapper for a TCAM module
//
// Dependencies:
//
// Revision:
// Revision 0.02 - Improved AXI4-Lite protocol handling
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi4_tcam_wrapper #(
parameter ADDR_WIDTH = 3,
parameter KEY_WIDTH = 4,
parameter DATA_WIDTH = 1,
parameter MASK_DISABLE = 1,
parameter RAM_STYLE_DATA = "block"
)
(
input wire clk,
input wire rst,
// AXI4-Lite interface signals
input wire [31:0] s_axi_awaddr,
input wire s_axi_awvalid,
output reg s_axi_awready,
input wire [31:0] s_axi_wdata,
input wire [3:0] s_axi_wstrb,
input wire s_axi_wvalid,
output reg s_axi_wready,
output reg [1:0] s_axi_bresp,
output reg s_axi_bvalid,
input wire s_axi_bready,
input wire [31:0] s_axi_araddr,
input wire s_axi_arvalid,
output reg s_axi_arready,
output reg [31:0] s_axi_rdata,
output reg [1:0] s_axi_rresp,
output reg s_axi_rvalid,
input wire s_axi_rready
);
// Internal signals
reg [ADDR_WIDTH-1:0] set_addr;
reg [DATA_WIDTH-1:0] set_data;
reg [KEY_WIDTH-1:0] set_key;
reg [KEY_WIDTH-1:0] set_xmask;
reg set_clr;
reg set_valid;
reg [KEY_WIDTH-1:0] req_key;
reg req_valid;
wire req_ready;
wire [ADDR_WIDTH-1:0] res_addr;
wire [DATA_WIDTH-1:0] res_data;
wire res_valid;
wire res_null;
// Reset handling
always @(posedge clk or posedge rst) begin
if (rst) begin
set_valid <= 0;
req_valid <= 0;
s_axi_awready <= 0;
s_axi_wready <= 0;
s_axi_bvalid <= 0;
s_axi_arready <= 0;
s_axi_rvalid <= 0;
end else begin
// Write transaction handling
if (s_axi_awvalid && !s_axi_awready) begin
s_axi_awready <= 1;
end else begin
s_axi_awready <= 0;
end
if (s_axi_wvalid && !s_axi_wready) begin
s_axi_wready <= 1;
set_addr <= s_axi_awaddr[ADDR_WIDTH-1:0];
set_data <= s_axi_wdata[DATA_WIDTH-1:0];
set_key <= s_axi_wdata[KEY_WIDTH+8-1:8]; // Adjusted bits for key
set_xmask <= s_axi_wdata[KEY_WIDTH-1:0];
set_clr <= s_axi_wdata[0];
set_valid <= 1;
end else begin
s_axi_wready <= 0;
set_valid <= 0;
end
if (s_axi_bready && s_axi_bvalid) begin
s_axi_bvalid <= 0;
end else if (set_valid) begin
s_axi_bvalid <= 1;
s_axi_bresp <= 2'b00; // OKAY response
end
// Read transaction handling
if (s_axi_arvalid && !s_axi_arready) begin
s_axi_arready <= 1;
req_key <= s_axi_araddr[KEY_WIDTH-1:0];
req_valid <= 1;
end else begin
s_axi_arready <= 0;
req_valid <= 0;
end
if (req_valid && req_ready) begin
s_axi_rvalid <= 1;
s_axi_rdata <= {24'd0, res_data};
s_axi_rresp <= 2'b00;
end else if (s_axi_rvalid && s_axi_rready) begin
s_axi_rvalid <= 0;
end
end
end
// Instantiate TCAM
tcam #(
.ADDR_WIDTH(ADDR_WIDTH),
.KEY_WIDTH(KEY_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MASK_DISABLE(MASK_DISABLE),
.RAM_STYLE_DATA(RAM_STYLE_DATA)
) tcam_inst (
.clk(clk),
.rst(rst),
.set_addr(set_addr),
.set_data(set_data),
.set_key(set_key),
.set_xmask(set_xmask),
.set_clr(set_clr),
.set_valid(set_valid),
.req_key(req_key),
.req_valid(req_valid),
.req_ready(req_ready),
.res_addr(res_addr),
.res_data(res_data),
.res_valid(res_valid),
.res_null(res_null)
);
endmodule
