Pynq z2 pin logic high by power on

hello I am using PYNQ Z2 to control my ASIC chip, there are two port to switch on the TX and RX. By the Power on duration and loading the overlay the two control pins are in logical High with 3.3 V.
It is horrible , if switch on the receiver at the same time open the transceiver.
If you can help me or if I can share your experience, I would be very grateful.


Welcome to PYNQ community.
This is not related to PYNQ but I am happy to share HW knowledge.
It is possible to add buffer between ASIC and FPGA?
This can be done easily on PL IO but not ARM MIO.
FPGA itself can pull-high / pull-low.
While to resolve the power on surge current. put a middle pull low resistor like 4k7 or 2k2.
This is good enough for your case.

However, the MIO itself I am not sure but a GPIO on MIO with pull-none or pull-low setting should do the same behavior.