Hi all,
I’m transmitting a 15 MHz OFDM signal through DAC 230 on an RFSoC4x2 using PYNQ + AXI DMA → RF Data Converter. The carrier shows up correctly at 100 MHz, but I’m getting two strong spurs at 50 MHz and 150 MHz, only ~23 dB below the carrier (see spectrum analyzer image).
Setup
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Board: RFSoC4x2, Vivado 2022.x, PYNQ
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DAC 230: Fs = 500 MSPS, Interpolation = 5×, Mixer = Fine (I/Q → Real), NCO = 100 MHz, Nyquist Zone 1, Inverse Sinc + Invert Q enabled
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IQ data: 100 MSPS, packed
{Q[15:0], I[15:0]}as uint32 -
AXI DMA: 64-bit M_AXIS_MM2S → SmartConnect → RFDC
s20_axis -
Samples per AXIS cycle (RFDC): 4
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Ref clocks: LMK = LMX = 500 MHzExpected: 15 MHz signal centered at 100 MHz, occupying 92.5–107.5 MHz.
Observed (spectrum analyzer):
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100 MHz @ −20.5 dBm (desired)
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150 MHz @ −43.6 dBm (spur)
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50 MHz @ −44.2 dBm (spur)
The baseband FFT of my buffer (before DMA) looks clean — signal at DC, ~15 MHz wide, noise floor ~−80 dBc. So the IQ data is fine; something is off in the RFDC datapath.
The spurs sit at exactly NCO ± Fs_iq/2, which looks like a first interpolation image. I suspect a stream-width mismatch: the RFDC expects 4 complex samples/beat (128 bits), but my DMA M_AXIS is only 64 bits = 2 complex samples/beat, so the effective IQ rate is 50 MSPS instead of 100 MSPS.
Questions
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For DAC at Fs = 500 MSPS, interp = 5×, 4 samples/cycle — does that mean 4 complex samples (128-bit AXIS) or 4 real?
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Is a 64-bit DMA → 4-sample/cycle RFDC the cause of the ±Fs_iq/2 images?
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Should I widen DMA to 128 bits, add a width converter, or reconfigure RFDC to 2 samples/cycle?
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Is “Invert Q Output” needed in I/Q → Real mode with standard {I + jQ} data?
Block design, RFDC config, DMA config, spectrum, and notebook attached. Any help appreciated!
Thanks.
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Jupyter_Notebook.pdf (244.1 KB)
