Server Connection Error - File Save Error design.ipynb

May 2024 - PYNQ Version
Board - RFSoC 4x2
Issue - I’ve built a Hardware Design where Programmable Logic can interface with DAC Channels on board the RFSoC 4x2 using Direct Memory Access. DMA is used to push symbols from PL DDR4 memory to the DAC path. I plan to view this on my oscilloscope as we are interested to observe processor emulation data on scope in future using this procedure. But, I have been facing error interfacing the DMA script from Base Overlay. The Jupyter Lab Server Connection keeps dropping off as it reattempts to connect but finally, it shows me “File Save Error for xxxx.ipynb” - failed to fetch. Surprisingly, for an older design that I worked on earlier it interfaces properly without dropping but for new designs it shows this problem. Facing this problem since past week, I’ve tried all sort of tricks and techniques but none have worked so far. Please help as soon as possible!


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Do you have to reset the board after the notebook hangs?
If so, can you try split up the cell and execute the code line by line to check if this happens at a particular point in your code?

You can hang the board if you access an invalid address. If this is happening, I’d suggest you check if your HWH is up-to-date with your .bit file. After that I would debug the hardware design (simulation first) to check it is working as expected.

Cathal

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Hey Cathal, Thank you for your response! This happens when I start to leverage DMA script to access the same from my hardware design. My Hardware works properly with simulation and bitstream generation is error and CW free.

Which line causes it to hang?
Did you check your HWH and BIT files?

Cathal

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It’s basically the overlay.axi_dma_0, last line in the picture.

How do I find discrepancy in .bit and .hwh files? Can you help me out, both files belong to the same project and is up-to-date if you mean by that.

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Yes, this is what I mean.

This is just variable assignment in software only - there is no interaction with the PL. I don’t know why this would cause your board to hang. I’d suggest trying a different SD card to make sure there isn’t a problem with the one you are using.

Cathal

Sure Cathal, I’ll give it a shot.

Hey @cathalmccabe , on an other note, could it be some Jupyter configuration issue? I know that there some 100 mb cap on data accessed/transfered through Jupyter Notebook but my design is having .bit file worth 33 MB plus the hwh file of 387 KB which is well below the limit.

I’m not aware of such a limit, so I don’t think this is the issue.

Cathal

I tried the same design on new SD Card with v3.0.1 PYNQ on RFSoC 4x2, it yields in the same Jupyter Server Connection Error. But, it does pass all the self tests etc. Very strange.

Hi,
Can you share the BIT, HWH, IPYNB files?
Cathal

Sure, Cathal. Sending it across shortly!

Here’s a compressed file -
DMA-DAC_Design.zip (600.8 KB)

Hello @cathalmccabe, any update from your tests? Is the design properly running on your end?