Timing warning in PYNQ-ZU design for CameraLink


I’m currently designing a Camera-Link IP for my PYNQ-ZU board. I’m using the FMC-CAMERALINK carrier board from Alpha Data to interface with a Photonfocus camera. I’m using as reference for the CameraLink reception the following application note.

The block design is provided below:
camera_link_pynq.pdf (108.7 KB)

I’m currently encountering the following timing critical warnings:

  • no common primary clock between related clocks (i’m assuming clk_pl_0 and clk_pl_1);
  • no common node between related clocks;
  • no common period between related clocks;
  • no input delay specified for the datain_p bus.

I’m assuming that there should be away to get rid of the first 3 by correctly setting the constraints but I don’t exactly know what to add.

For the last point, I’m trying to get some information from the other application note and by using the Excel sheet calculator from the reference design but it didn’t help me too much since I don’t know exactly what to look for.

For reference, the Photonfocus I’m trying to connect to uses a base camera link interface, px_clk = 80 MHz.

Let me know if other reports are needed.

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After reading the two application notes a little more in detail, I noticed that by using set_false_path on input data and clock ports to the ISERDES instances, all warnings are fixed. According to the reference design:

  • Certain paths within the receiver are not required to be timed, and should be marked as a
    false path to achieve timing closure.

In the original reference design all nets connected to the input ISERDES instances are set as false paths. Apparently in my design this was not enforced accordingly so I fixed it in the constraints.

I’ll wait for a reply for somebody else for confirmation in case I’m wrong.



I’ll take advantage of this thread to report my progress and ask a question. Timing constraints have all been meet in respect to clocks and I made good progress on implementing a CL->AXI-Stream bridge for the incoming data. Right now I’m setting from the XDC that the CameraLink data and serial pins for communicating with the device as false paths, since Vivado reported a critical warning due to missing input/output delays.

Could this be a cause for concern? Should I make up some numbers? I unfortunately do not have any
reference as to the physical delays of the mezzanine card I intend to use to connect to my camera.

Thanks in advance for the help.



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I managed to generate the relevant files for my IP (bitstream, block design tcl and HWH). I loaded everything on the PYNQ-ZU and launched the following lines:

from pynq import Overlay

overlay = Overlay('./camera_link_pynq.bit')

Of course all files are placed in the same folder where the notebook where I’m loading the overlay is.
After trying to download the bitstream, the board just crashes.

This is the full block design:

What’s going on exactly?

EDIT: forgot to mention: PYNQ version is 2.7.0
Design generated with Vivado 2023.1

I suspect that this PYNQ version does not support projects generated with this Vivado version…

EDIT: after updating to PYNQ 3.0.1 the Overlay is loaded correctly

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