I implemented a design on ZCU111 in which I transfer a pulse train through the DAC and then loop back to the ADC for capturing. The issue is that in each DMA transfer, the waveform looks very unstable as shown below:
The pulses are periodic but as can be seen on the data capture screen, not only they are not periodic, the waveform time length also varies randomly and gets narrow.
When I capture the signal on oscilloscope, the waveform is fine. Thus, the issue is on my ADC data path. Figure below is the hardware block diagram I implemented in Vivado:
My RFDC converter settings are as follows:
The ADC clock out from the RFDC IP is 16MHz that I use that to derive both m0_axis_aclk as well as the FIFO Data Stream Write. The FIFO Data Stream Read operates with the processor clock at 249.997498MHz.
Both ADC and DAC sampling rates are 1.024 GHz.
Basically, the problem is that the captured waveform is unstable. It’s like untriggered signal on oscilloscope. I tried to implement a trigger mechanism on the FPGA by writing the following verilog module and adding right after the data stream from the RFDC IP:
module adctrig #(parameter DATA_WIDTH = 16)
input [DATA_WIDTH-1:0] s_axis_data,
output reg m_axis_valid,
output reg [DATA_WIDTH-1:0] m_axis_data,
reg flag = 1’b0;
assign s_axis_ready = m_axis_ready;
always @ (posedge axis_clk) begin if (flag == 1) begin m_axis_data <= s_axis_data; end else if (trigger_in == 1 && flag == 0) begin flag <= 1'b1; end end always @(posedge axis_clk) begin m_axis_valid <= s_axis_valid & s_axis_ready; end
Any comments or feedback or similar experience would be appreciated. Thank you!