Is there a way to find out the wiring length in a Pynq-z1 circuit board?
I am trying to send 12-bit signals in parallel at 160 MHz from a GPIO pin to an external board, and I want to match the signal timing as closely as possible.
I found the URL for the schematic (link bellow), but cannot find the artwork data.
- Pynq-Z1 board, Image 3.0.1
I don’t think this info is available. I think 160MHz over the GPIO pins would be quite challenging as the connectors are designed for high speed. Could you use the HDMI interface? This port is connected directly to FPGA pins.
No it won’t work even on HDMI TMDS D0-2 + CLK = 8 pins unless the signal traces are length matched.
The board files should be open:
Use PL IO to enable dual edge triggered IO aka DDR so clock runs @ 80MHz.
Thank you for your replies. I understand 160MHz is too challenging.
I will try PL IO with DDR in 80MHz.
I was unaware that HDMI is accessible for general purposes.
In my project, due to insufficient GPIO, I contemplate utilizing HDMI as an additional GPIO resource.
What Cath proposed is that HDMI uses differential pairs and no additional translator is used in this board which is simply said as PL IO_P IO_N. So you can use HDMI connector to connect in such way.
But the problem is that the HDMI to GPIO adapter would require additional hardware design which means no matter how it is still tedious.
So a simpler solution from my point of view is that double edge flops are available and way bother on single edge 160MHz design.
HDMI uses TMDS which also undergo double edge 742.5MHz trigger flops designs so you can do internal flop retiming without trace matching on 80MHz more easier than 160MHz. =]
I express my gratitude for your responses. Thus, if I comprehend correctly, you suggest that multiplying 80MHz by 2, employing double-edge flops, will yield a frequency of 160MHz, which proves to be a simpler alternative to utilizing HDMI. I intend to gauge the extent of wiring with the aid of a ruler and strive to align the timing accordingly. Nevertheless, I hold optimism that the Pynq designer shall eventually divulge the wiring length.
You don’t need tight length matching as you are retiming inside the FPGA itself. When setup time is eased hold time is what you need to take care.
80MHz on double edge flops mean a data sampled @ 160MHz 80MHz high+low pulse sampling = freq*2.
But one big new to young players as David always mentioned if these IO are not in the same bank then you are not allow to use internal IO retiming don’t ask me why this is the case but that is what I had encounter in over 250MHz design ADDA all high speed signal group must be same BANK =[
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