PYNQ: PYTHON PRODUCTIVITY

ZCU104 - Custom Overlay Cannot HDL Wrapper

Hi, I followed Overlay Tutorial with aid video to create a custom overlay.
The tutorial is base on PYNQ-Z1, and my platform is ZCU104.
I can create Add IP by Vivado-HLS 2020.1 successfully.
After that, I need to add an IP for Block Design on Vivado 2020.1.
The tutorial selected ZYNQ7 Processing System.
I selected Zynq UltraScale+ MPSoC instead, because my platform is ZCU104.

And then add Add IP into it -> Create HDL Wrapper -> Select Let Vivado manage wrapper and auto-update.
However, it showed error…

Except the Block Design IP, I used identical setting according to the tutorial video.
Because I don’t have any knowledge for verilog, don’t know how to solve it…

Is the issue in the Block Design IP or else?
Any help will be highly appreciated!

The error is telling you a clock pin is not connected properly.

Can you post a picture of your block diagram? The error messages are obscuring the block diagram. The hpm1_fpd_aclk pin is right underneath the error messages.

I’d guess that it is unconnected, and that you need to connect it to a PS clock pin. This could be the same wire that is connected to ap_clk on your IP.

Cathal

1 Like

Dear Cathal:
Thanks for your reply quickly!

I’d guess that it is unconnected, and that you need to connect it to a PS clock pin. This could be the same wire that is connected to ap_clk on your IP.

You’re right! The maxihpm1_fpd_aclk don’t connect to anything.
After connecting it to ap_clk, it can Create HDL Wrapper, bitstream & tcl file!

Many thanks for your help:D